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[VHDL-FPGA-Verilog] UART

Description: 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
Platform: | Size: 1106944 | Author: xiao cao | Hits:

[VHDL-FPGA-Verilog] fpga.fifo

Description: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Platform: | Size: 81920 | Author: 雷志 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: FIFO程序，适用FPGA仿真的代码，有一定的价值-FIFO
Platform: | Size: 3072 | Author: 陈一可 | Hits:

[VHDL-FPGA-Verilog] fifo_test.v.tar

Description: code for implementing high speed fifo for apturing data from fpga-code for for implementing high speed fifo for apturing data from fpga
Platform: | Size: 2048 | Author: Vikas | Hits:

[ARM-PowerPC-ColdFire-MIPS] fifo

Description: 用FPGA做的fifo，源码，调试通过，有工程和波形文件-FPGA to do with the fifo, source code, debugging through, there are engineering and waveform file
Platform: | Size: 354304 | Author: 马泽龙 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
Platform: | Size: 164864 | Author: Daisy | Hits:

[Other] FIFO

Description: fifo的实现，可以作用于memory的数据传输等地方，在fpga上实现，可以进行综合和仿真-fifo implementation, you can act on memory data transfer and other places, in the fpga to achieve, to undertake a comprehensive and Simulation
Platform: | Size: 6144 | Author: zz | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 设计了一个具有双时钟信号，双复位信号的FIFO，用于FPGA中的数据缓冲，RAM的定义是参数型，可以根据自己的需求，修改此参数，完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this parameter, the completion of the capacity expansion of RAM. Procedures described in detail
Platform: | Size: 183296 | Author: luosheng | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: 结合FPGA和以太网传输的特点，设计了一套数据采集系统，应用FPGA的内部逻辑实现对ADC、SDRAM、网卡控制芯片DM9000的时序控制，以FPGA作为采集系统的核心，通过ADC，将采集到的数据存储到SDRAM中，以FIFO方式从SDRAM中读出数据，并将数据结果通过以太网接口传输到计算机-Combination of FPGA and Ethernet features, designed a data acquisition system, application FPGA' s internal logic to realize the ADC, SDRAM, LAN controller chip DM9000 timing control to capture FPGA as the core of the system, through the ADC, will be collected The data stored in SDRAM, the SDRAM in order to read data from the FIFO method, and data results to a computer via Ethernet interface
Platform: | Size: 388096 | Author: gdr | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FIFO control in the FPGA-FIFO control in the FPGA
Platform: | Size: 671744 | Author: 孙林 | Hits:

[VHDL-FPGA-Verilog] sfifo

Description: verilog编写的同步FIFO，功能仿真完全正确，大家可以参考下。-verilog write synchronization FIFO, functional simulation completely correct, we can refer to the next.
Platform: | Size: 1024 | Author: 查乐 | Hits:

[VHDL-FPGA-Verilog] async-FIFO

Description: 采用VHDL实现异步的FIFO程序，是学习FPGA的重点内容-VHDL implementation using asynchronous FIFO procedures, the key elements to learn FPGA! !
Platform: | Size: 220160 | Author: yihoumei | Hits:

[VHDL-FPGA-Verilog] FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta

Description: FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
Platform: | Size: 16619520 | Author: Aleks | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 基于fpga的fifo的设计与实现，好东西，希望大家喜欢-Fpga-based design and implementation of fifo, good things, hope you like
Platform: | Size: 157696 | Author: 杜 | Hits:

[VHDL-FPGA-Verilog] Pipeline-and-FIFO

Description: Pipeline and FIFO的FPGA设计-Pipeline and FIFO FPGA design
Platform: | Size: 9216 | Author: sun | Hits:

[Other] asynchronous-FIFO-FPGA

Description: 基于FPGA的异步FIFO设计,值得参考一下，希望对你有所帮助- asynchronous FIFO design based on FPGA
Platform: | Size: 185344 | Author: 范鹏 | Hits:

[Other] FIFO

Description: FPGA实现的FIFO资料汇总，全面学习FIFO-FPGA implementation FIFO data aggregation, comprehensive study FIFO
Platform: | Size: 8335360 | Author: 李志 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 基于FPGA的fifo例程及仿真测试文件。-Fifo FPGA-based emulation routines and test files.
Platform: | Size: 10864640 | Author: 金慧宇 | Hits:

[VHDL-FPGA-Verilog] FPGA-Source-Code_VHDL

Description: cypress fx2lp slave fifo fpga控制端源码-source code of FX2LP_SLAVE_FIFO CONTROLLER S
Platform: | Size: 1172480 | Author: 赵 | Hits:

[VHDL-FPGA-Verilog] 带FIFO的ov7670 FPGA应用程序，经测试可用

Description: 这是用Verilog编写的OV7670摄像头驱动代码，带FIFO，经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)
Platform: | Size: 1683456 | Author: jomair | Hits:
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